Also known as control electronics · FPGA · arbitrary waveform generator · AWG · real-time control · control stack · control system · signal chain
Control hardware is the classical machinery between an optimized pulse and the qubit: waveform generators and
synthesizers, cables, filters and amplifiers, digitizers, FPGAs that make real-time decisions, and the software stack
that schedules and calibrates everything [1]. Its properties — bandwidth, resolution, latency,
noise, distortion, channel count — are constraints that every optimal-control problem inherits. As processors grow,
the electronics become a scaling problem in their own right.
From waveform to qubit
Generating pulses. Pulses are usually synthesized at baseband by arbitrary waveform generators and mixed up to
the qubit frequency. RF system-on-chip devices can now synthesize carriers of several GHz directly. One open
design, QICK, reached 99.93% average gate fidelity on a transmon [2].
Bandwidth and resolution. Sample rates and filters limit how fast pulses can change, and the resolution of the
converters limits how precisely they are set. These limits enter optimal control as constraints or through a
parametrization in smooth functions; see Pulse parametrization & constraints. Hardware nonlinearities can be included in the
optimization itself [3].
Distortion. Cables and filters distort pulses before they reach the device. The qubit can measure the
distortion, of microwave pulses [4] or of flux pulses [5], and the
measured response can be pre-compensated. The qubit can also act as a vector network analyser of its own control
line [6]. See System identification for control.
Real-time control and feedback
Error correction, feedback and adaptive protocols need decisions within a fraction of the coherence time. Dedicated
hardware and gateware feed qubit measurement results back or forward in real time [7]. FPGA-based
signal processing demodulates readout, assigns the qubit state and triggers feedback with a latency of about 110 ns
[8]. Below-threshold surface-code memories ran with a real-time decoder [9], and
neural-network agents have acted on qubits in real time from FPGAs [10]. Modular, open FPGA
systems such as QubiC give full access to the control stack [11]. See Measurement-based feedback and
Control for quantum error correction.
Scaling the interface
Every qubit in a dilution refrigerator needs control and readout lines from room temperature. With millions of qubits
the wiring cannot scale, so control electronics are moving closer to the qubits.
Cryogenic CMOS. Cryo-CMOS circuits are designed for operation at a few kelvin [12]. A 28-nm
cryogenic controller for transmons dissipates less than 2 mW at 3 K [13]. Cryogenic CMOS has
controlled silicon spin qubits [14].
Superconducting logic. Single-flux-quantum circuits could drive qubits directly with bitstreams derived from
optimal control, measured by a Josephson photon counter at the millikelvin stage [15].
Such controllers offer fewer degrees of freedom than room-temperature instruments. The 28-nm controller, for example,
implements a 16-word instruction set of XY gates [13], which restricts the pulses that optimal
control can use.
Software stacks
Above the electronics sits software that compiles circuits into pulse schedules, calibrates them and analyses
results. It includes pulse-level languages [16], calibration frameworks [17] and tools
that combine control, characterization and optimization [18]. See Pulse-level compilation and
Closed-loop & in-situ optimization.
Limitations
Pulses optimized without the true transfer function of the signal chain fail on hardware, and that transfer
function drifts with temperature and time.
Latency adds up from readout, digitization, decision and pulse generation, and limits feedback speed whatever the
qubit.
Low-power cryogenic electronics trade flexibility and precision for scalability, and their noise can couple into
the qubits.
Key papers
David J ReillyEngineering the quantum-classical interface of solid-state qubitsnpj Quantum Inf1, 15011 (2015)doi
Review of the quantum–classical interface of solid-state qubits — the electronics that control and read them.
Colm A. Ryan, Blake R. Johnson, Diego Ristè, Brian Donovan and Thomas A. OhkiHardware for dynamic quantum computingReview of Scientific Instruments88, 104703 (2017)doi
Hardware, gateware and software for dynamic experiments with real-time feedback and feed-forward.
Yves Salathé, Philipp Kurpiers, Thomas Karg, Christian Lang, Christian Kraglund Andersen, et al.Low-Latency Digital Signal Processing for Feedback and Feedforward in Quantum Computing and CommunicationPhys. Rev. Applied9, 034011 (2018)doi
FPGA signal processing that turns readout into feedback triggers with low latency.
Leandro Stefanazzi, Kenneth Treptow, Neal Wilcer, Chris Stoughton, Collin Bradford, et al.The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectorsReview of Scientific Instruments93, 044709 (2022)doi
QICK, an open-source RFSoC-based controller that synthesizes multi-GHz pulses directly.
Xiao Xue, Bishnu Patra, Jeroen P. G. van Dijk, Nodar Samkharadze, Sushil Subramanian, et al.CMOS-based cryogenic control of silicon quantum circuitsNature593, 205-210 (2021)doi
Cryogenic CMOS control of silicon qubits, a step toward integrating electronics next to the qubits.
M. A. Rol, L. Ciorciaro, F. K. Malinowski, B. M. Tarasinski, R. E. Sagastizabal, et al.Time-domain characterization and correction of on-chip distortion of control pulses in a quantum processorApplied Physics Letters116, 054001 (2020)doi
Measuring and compensating distortions of flux-control pulses with the qubit itself.
Software
QICK — firmware and software for RFSoC-based qubit control and readout
Qibolab — hardware drivers and pulse execution for several control electronics platforms
References
David J ReillyEngineering the quantum-classical interface of solid-state qubitsnpj Quantum Inf1, 15011 (2015)doi
Leandro Stefanazzi, Kenneth Treptow, Neal Wilcer, Chris Stoughton, Collin Bradford, et al.The QICK (Quantum Instrumentation Control Kit): Readout and control for qubits and detectorsReview of Scientific Instruments93, 044709 (2022)doi
I. N. Hincks, C. E. Granade, T. W. Borneman and D. G. CoryControlling Quantum Devices with Nonlinear HardwarePhys. Rev. Applied4, 024012 (2015)doi
Simon Gustavsson, Olger Zwier, Jonas Bylander, Fei Yan, Fumiki Yoshihara, et al.Improving Quantum Gate Fidelities by Using a Qubit to Measure Microwave Pulse DistortionsPhys. Rev. Lett.110, 040502 (2013)doi
M. A. Rol, L. Ciorciaro, F. K. Malinowski, B. M. Tarasinski, R. E. Sagastizabal, et al.Time-domain characterization and correction of on-chip distortion of control pulses in a quantum processorApplied Physics Letters116, 054001 (2020)doi
Markus Jerger, Anatoly Kulikov, Zénon Vasselin and Arkady FedorovIn Situ Characterization of Qubit Control Lines: A Qubit as a Vector Network AnalyzerPhys. Rev. Lett.123, 150501 (2019)doi
Colm A. Ryan, Blake R. Johnson, Diego Ristè, Brian Donovan and Thomas A. OhkiHardware for dynamic quantum computingReview of Scientific Instruments88, 104703 (2017)doi
Yves Salathé, Philipp Kurpiers, Thomas Karg, Christian Lang, Christian Kraglund Andersen, et al.Low-Latency Digital Signal Processing for Feedback and Feedforward in Quantum Computing and CommunicationPhys. Rev. Applied9, 034011 (2018)doi
Google Quantum AI and Collaborators, Rajeev Acharya, Dmitry A. Abanin, Laleh Aghababaie-Beni, Igor Aleiner, et al.Quantum error correction below the surface code thresholdNature638, 920-926 (2025)doi
Kevin Reuer, Jonas Landgraf, Thomas Fösel, James O’Sullivan, Liberto Beltrán, et al.Realizing a deep reinforcement learning agent for real-time quantum feedbackNat Commun14, 7138 (2023)doi
Yilun Xu, Gang Huang, Jan Balewski, Ravi Naik, Alexis Morvan, et al.QubiC: An Open-Source FPGA-Based Control and Measurement System for Superconducting Quantum Information ProcessorsIEEE Trans. Quantum Eng.2, 1-11 (2021)doi
Bishnu Patra, Rosario M. Incandela, Jeroen P. G. van Dijk, Harald A. R. Homulle, Lin Song, et al.Cryo-CMOS Circuits and Systems for Quantum Computing ApplicationsIEEE J. Solid-State Circuits53, 309-321 (2018)doi
Joseph C. Bardin, Ted White, Marissa Giustina, Kevin J. Satzinger, Kunal Arya, et al.Design and Characterization of a 28-nm Bulk-CMOS Cryogenic Quantum Controller Dissipating Less Than 2 mW at 3 KIEEE J. Solid-State Circuits54, 3043-3060 (2019)doi
Xiao Xue, Bishnu Patra, Jeroen P. G. van Dijk, Nodar Samkharadze, Sushil Subramanian, et al.CMOS-based cryogenic control of silicon quantum circuitsNature593, 205-210 (2021)doi
R McDermott, M G Vavilov, B L T Plourde, F K Wilhelm, P J Liebermann, et al.Quantum–classical interface based on single flux quantum digital logicQuantum Sci. Technol.3, 024004 (2018)doi
Andrew Cross, Ali Javadi-Abhari, Thomas Alexander, Niel De Beaudrap, Lev S. Bishop, et al.OpenQASM 3: A Broader and Deeper Quantum Assembly LanguageACM Transactions on Quantum Computing3, 1-50 (2022)doi
Nicolas Wittler, Federico Roy, Kevin Pack, Max Werninghaus, Anurag Saha Roy, et al.Integrated Tool Set for Control, Calibration, and Characterization of Quantum Devices Applied to Superconducting QubitsPhys. Rev. Applied15, 034080 (2021)doi
Harrison Ball, Michael J Biercuk, Andre R R Carvalho, Jiayin Chen, Michael Hush, et al.Software tools for quantum control: improving quantum computer performance through noise and error suppressionQuantum Sci. Technol.6, 044011 (2021)doi
Recent papers
111 tracked papers since 2000 are classified
under this topic. See all ·
Feed
Scaling fault-tolerant quantum computing (FTQC) requires orchestrating millions of operations continuously across a tightly coupled classical-quantum control stack. A critical challenge in this orchestration is determining the optimal hardware-software boundary, i.e., the Quantum Instruction Set Architecture (QISA). We focus on cryogenic, fixed-connectivity qubit platforms, such as superconducting and topological Majorana qubits. For these, existing QISA choices either operate at too low a level, violating cryogenic thermal budgets at scale, or at too high a level, imposing unrealizable complexity on the control engine. To reason about these tradeoffs, we introduce the ARIES instruction set hierarchy, which categorizes QISAs into distinct abstraction levels. To systematically evaluate these levels, we develop an end-to-end evaluation toolflow featuring a cycle-accurate classical driver and hardware engine simulator. Using eight quantum applications across superconducting and topological qubit platforms, we measure instruction bandwidth, transceiver power dissipation, and measurement processing overheads. We demonstrate that while physical-level abstractions exceed the thermal limits of dilution refrigerators by orders of magnitude, canonical-level abstractions significantly underestimate hardware routing congestion and execution runtimes. Our Level 4 QISA (local logical operations) offers an optimal architectural balance. As quantum hardware platforms scale toward FTQC in the coming years, our findings provide concrete architectural guidance for the design of their classical control stacks and instruction interfaces.
The QICK (Quantum Instrumentation Control Kit), first introduced in 2022, is a standalone open source control system for quantum information science. Since then, QICK has been migrated to new hardware platforms, expanded its functionality for applications with different types of qubits (superconducting, atomic, ion-trapped, and spin defects), as well as quantum sensors, and quantum networks. QICK is a highly optimized control kit, with a library of functions that can be used for more than one application. In particular, the software and firmware are customized to minimize latency and maximize control performance and throughput. In this white paper, we describe hardware details and performance of the QICK Box. The QICK Box features up to 16 outputs, up to 8 inputs, and 8 20-bit DC biases. Modular output and input daughtercards give the choice of signal chains optimized for fast DC-coupled signals or RF signals up to 10 GHz. Power levels, step attenuation, and bandpass filtering are controlled by software. We demonstrate the system's performance through single-shot readout measurements of a six-transmon device at the Quantum Underground Instrumentation Experimental Testbed (QUIET) at Fermilab, achieving (91.7 +/- 0.4)% readout fidelity limited by T1 decay during the readout. The single shot readout signal-to-noise ratio (SNR) is 4.4 +/- 0.1 without a quantum amplifier, confirming that the QICK Box is suitable for high-fidelity quantum control and measurement applications. Advances in firmware and software will be described in a separate paper.
Fast and accurate qubit-state assignment is essential for feedback, calibration, and error correction in quantum processors. In superconducting platforms, frequency-multiplexed readout makes this task intrinsically multivariate as measured traces can encode crosstalk, qubit-state relaxation events, and other transient nonidealities that are not fully captured by conventional matched filtering. Here, we introduce spiking neural network (SNN) discriminators for superconducting qubit readout. By processing the measurement window in successive time chunks, the networks exploit temporal structure and update classification scores as data arrive, rather than waiting until the end of the readout window. The spiking networks outperform matched-filter discrimination and approach the accuracy of a full-trace artificial neural network. Beyond reaching the performance of artificial neural networks, the key advantage of SNNs is that they provide a streaming, time-resolved estimate of the qubit state that evolves as the readout signal is acquired. Using quantisation-aware training and hls4ml synthesis, we further demonstrate that each FPGA inference update can be completed before the next readout chunk arrives. These results establish spiking neural networks as a promising route to low-latency, real-time qubit readout on FPGA hardware, with broader implications for time-critical quantum-control and scientific-inference applications.
Real-time waveform generation supports dynamic quantum circuits without pre-storing complete waveforms for every execution path. However, long-lived distortions in flux-control lines degrade gate fidelity, requiring compensation to account for the actual pulse history. A frequency-domain inversion and time-domain fitting method is proposed for resource-efficient real-time flux distortion compensation. The method fits the reconstructed compensation impulse response with a compact hybrid infinite impulse response (IIR) and finite impulse response (FIR) filter. Look-ahead parallelization enables this filter to process synthesized waveforms at 1.2GSa/s on a field-programmable gate array (FPGA). Two-qubit cross-entropy benchmarking shows that real-time IIR filtering achieves a median controlled-Z Pauli fidelity close to the software-reference value of 99.57%. Numerical analysis and FPGA synthesis indicate approximately logarithmic growth in hardware resource use with compensation timescale. Extending compensation from microsecond to hundred-microsecond timescales increases look-up table (LUT) and digital signal processing (DSP) resource use by only about 14% and 4%, respectively, while maintaining a relative arithmetic error below $10^{-4}$. This work provides a scalable hardware foundation for high-fidelity flux control in dynamic superconducting quantum circuits.
Measurement-responsive quantum experiments require control programs that can revise future operations after execution has begun without disturbing events already committed to precise timing. We present Time-Deterministic and Instruction-Dynamic Execution (TIDE), an FPGA quantum-control processor that separates a runtime-revisable future from a hardware-timed committed-event stream. TIDE provides two complementary update paths: Dynamic Instruction Parameter Update (DIPU) applies a one-shot patch to the next matching event before parameter capture, while Dynamic Instruction Stream Overwrite (DISO) performs guarded replacement, logical deletion, and out-of-line insertion in future resident-program regions. Per-channel committed-event FIFOs isolate accepted descriptors from subsequent control-core and update activity. The implemented Xilinx ZCU102 design meets timing at 250 MHz for the control core and 425 MHz for the timing/update domain. With downstream ready, every tested descriptor committed at least one timing-domain cycle before its programmed timestamp was dispatched in the programmed cycle at the registered output interfaces. In separate post-commit tests, committed timestamps and payloads remained unchanged under the applied perturbations. The minimum all-success mapped DIPU margin was four 250 MHz control-domain cycles. Under continuous payload delivery, an L-word contiguous overwrite completed in L+5 update-domain cycles. Within the characterized guard-distance range, rejected DISO requests preserved the resident path, whereas all admitted replacement, deletion, and insertion transactions exercised here executed a complete revised sequence. TIDE therefore enables runtime adaptation of both parameters and instruction structure while preserving deterministic service of committed quantum-control events.