Quantum control papers on arXiv, selected and classified automatically by QOC. https://llorebaga.github.io/QOC/topics/control-hardware/ 2026-10-12T00:00:00Z QOC https://arxiv.org/abs/2610.17058 2026-10-12T00:00:00Z 2026-10-12T00:00:00Z Dmitry FilippovJustin HogaboamMathias SoekenRaghu GattaPrakash MuraliMatthias Troyer

Scaling fault-tolerant quantum computing (FTQC) requires orchestrating millions of operations continuously across a tightly coupled classical-quantum control stack. A critical challenge in this orchestration is determining the optimal hardware-software boundary, i.e., the Quantum Instruction Set Architecture (QISA). We focus on cryogenic, fixed-connectivity qubit platforms, such as superconducting and topological Majorana qubits. For these, existing QISA choices either operate at too low a level, violating cryogenic thermal budgets at scale, or at too high a level, imposing unrealizable complexity on the control engine. To reason about these tradeoffs, we introduce the ARIES instruction set hierarchy, which categorizes QISAs into distinct abstraction levels. To systematically evaluate these levels, we develop an end-to-end evaluation toolflow featuring a cycle-accurate classical driver and hardware engine simulator. Using eight quantum applications across superconducting and topological qubit platforms, we measure instruction bandwidth, transceiver power dissipation, and measurement processing overheads. We demonstrate that while physical-level abstractions exceed the thermal limits of dilution refrigerators by orders of magnitude, canonical-level abstractions significantly underestimate hardware routing congestion and execution runtimes. Our Level 4 QISA (local logical operations) offers an optimal architectural balance. As quantum hardware platforms scale toward FTQC in the coming years, our findings provide concrete architectural guidance for the design of their classical control stacks and instruction interfaces.

https://arxiv.org/abs/2610.03609 2026-10-02T00:00:00Z 2026-10-02T00:00:00Z Luis H. ArnaldiDiego MartinSara SussmanSho UemuraK. TreptowNeal WilcerA. Colón CesaníO. SeidelK. AnyangG. BratrudF. AbouzahrJ. Christiansen-SalamehD. BaxterGustavo Cancelo

The QICK (Quantum Instrumentation Control Kit), first introduced in 2022, is a standalone open source control system for quantum information science. Since then, QICK has been migrated to new hardware platforms, expanded its functionality for applications with different types of qubits (superconducting, atomic, ion-trapped, and spin defects), as well as quantum sensors, and quantum networks. QICK is a highly optimized control kit, with a library of functions that can be used for more than one application. In particular, the software and firmware are customized to minimize latency and maximize control performance and throughput. In this white paper, we describe hardware details and performance of the QICK Box. The QICK Box features up to 16 outputs, up to 8 inputs, and 8 20-bit DC biases. Modular output and input daughtercards give the choice of signal chains optimized for fast DC-coupled signals or RF signals up to 10 GHz. Power levels, step attenuation, and bandpass filtering are controlled by software. We demonstrate the system's performance through single-shot readout measurements of a six-transmon device at the Quantum Underground Instrumentation Experimental Testbed (QUIET) at Fermilab, achieving (91.7 +/- 0.4)% readout fidelity limited by T1 decay during the readout. The single shot readout signal-to-noise ratio (SNR) is 4.4 +/- 0.1 without a quantum amplifier, confirming that the QICK Box is suitable for high-fidelity quantum control and measurement applications. Advances in firmware and software will be described in a separate paper.

https://arxiv.org/abs/2610.02129 2026-10-01T00:00:00Z 2026-10-01T00:00:00Z Barry M. DillonAqib JavedJim HarkinPatryk DabkowskiBenjamin Lienhard

Fast and accurate qubit-state assignment is essential for feedback, calibration, and error correction in quantum processors. In superconducting platforms, frequency-multiplexed readout makes this task intrinsically multivariate as measured traces can encode crosstalk, qubit-state relaxation events, and other transient nonidealities that are not fully captured by conventional matched filtering. Here, we introduce spiking neural network (SNN) discriminators for superconducting qubit readout. By processing the measurement window in successive time chunks, the networks exploit temporal structure and update classification scores as data arrive, rather than waiting until the end of the readout window. The spiking networks outperform matched-filter discrimination and approach the accuracy of a full-trace artificial neural network. Beyond reaching the performance of artificial neural networks, the key advantage of SNNs is that they provide a streaming, time-resolved estimate of the qubit state that evolves as the readout signal is acquired. Using quantisation-aware training and hls4ml synthesis, we further demonstrate that each FPGA inference update can be completed before the next readout chunk arrives. These results establish spiking neural networks as a promising route to low-latency, real-time qubit readout on FPGA hardware, with broader implications for time-critical quantum-control and scientific-inference applications.

https://arxiv.org/abs/2609.27456 2026-09-23T00:00:00Z 2026-09-23T00:00:00Z Qi ZhouZi-Hao MeiPeng DuanPeng WangLiang-Liang GuoHao-Ran TaoWei-Cheng KongHui YangGuo-Ping GuoZhao-Yun Chen

Real-time waveform generation supports dynamic quantum circuits without pre-storing complete waveforms for every execution path. However, long-lived distortions in flux-control lines degrade gate fidelity, requiring compensation to account for the actual pulse history. A frequency-domain inversion and time-domain fitting method is proposed for resource-efficient real-time flux distortion compensation. The method fits the reconstructed compensation impulse response with a compact hybrid infinite impulse response (IIR) and finite impulse response (FIR) filter. Look-ahead parallelization enables this filter to process synthesized waveforms at 1.2GSa/s on a field-programmable gate array (FPGA). Two-qubit cross-entropy benchmarking shows that real-time IIR filtering achieves a median controlled-Z Pauli fidelity close to the software-reference value of 99.57%. Numerical analysis and FPGA synthesis indicate approximately logarithmic growth in hardware resource use with compensation timescale. Extending compensation from microsecond to hundred-microsecond timescales increases look-up table (LUT) and digital signal processing (DSP) resource use by only about 14% and 4%, respectively, while maintaining a relative arithmetic error below $10^{-4}$. This work provides a scalable hardware foundation for high-fidelity flux control in dynamic superconducting quantum circuits.

https://arxiv.org/abs/2608.15173 2026-08-15T00:00:00Z 2026-08-15T00:00:00Z Xiaoqin LuoJiayun SongXiaolu Su

Measurement-responsive quantum experiments require control programs that can revise future operations after execution has begun without disturbing events already committed to precise timing. We present Time-Deterministic and Instruction-Dynamic Execution (TIDE), an FPGA quantum-control processor that separates a runtime-revisable future from a hardware-timed committed-event stream. TIDE provides two complementary update paths: Dynamic Instruction Parameter Update (DIPU) applies a one-shot patch to the next matching event before parameter capture, while Dynamic Instruction Stream Overwrite (DISO) performs guarded replacement, logical deletion, and out-of-line insertion in future resident-program regions. Per-channel committed-event FIFOs isolate accepted descriptors from subsequent control-core and update activity. The implemented Xilinx ZCU102 design meets timing at 250 MHz for the control core and 425 MHz for the timing/update domain. With downstream ready, every tested descriptor committed at least one timing-domain cycle before its programmed timestamp was dispatched in the programmed cycle at the registered output interfaces. In separate post-commit tests, committed timestamps and payloads remained unchanged under the applied perturbations. The minimum all-success mapped DIPU margin was four 250 MHz control-domain cycles. Under continuous payload delivery, an L-word contiguous overwrite completed in L+5 update-domain cycles. Within the characterized guard-distance range, rejected DISO requests preserved the resident path, whereas all admitted replacement, deletion, and insertion transactions exercised here executed a complete revised sequence. TIDE therefore enables runtime adaptation of both parameters and instruction structure while preserving deterministic service of committed quantum-control events.

https://arxiv.org/abs/2608.06875 2026-08-07T00:00:00Z 2026-08-07T00:00:00Z Heyue LiYanshu GuoQichun LiuTie-Fu LiZhihua WangHanjun Jiang

Scalable quantum processors require control, readout, feedback, calibration, and error correction to coexist under bounded latency and shared-resource constraints, whereas existing platforms typically optimize only a subset of these capabilities. This article presents QCORE (Quantum-Control-Oriented Real-Time Execution), a QPU-side digital control reference architecture positioned between the Host and a platform-specific analog/mixed-signal front end. QCORE separates task management, shared resources, hard-real-time execution, and long-timescale services into four hardware partitions. A fast-result sideband closes same-round feedback, a Measurement Packet provides a traceable measurement and service interface, and a common service-control skeleton, Tile-local QEC, and versioned safe-point commit organize calibration, error correction, and long-term state updates. Transaction-level, event-driven, and quantum-behavioral models are used for evaluation. At a background load of 0.8, the $P_{99}$ latency of the shared Measurement Packet/Event feedback path is $(1.984\pm0.004)L_{\max}$. Closed-loop operation reduces the mean frequency error by $83.2\%\pm0.8\%$ and lowers the state-assignment error at maximum readout drift from $10.39\%\pm0.54\%$ to $5.37\%\pm0.29\%$. No unsafe acceptance or mixed-version observation is observed in 100,000 configuration transactions, and Tile-local QEC reduces modeled global-boundary demand and yields a $2.08\times$ capacity-normalized scaling estimate.

https://arxiv.org/abs/2607.07372 2026-07-08T00:00:00Z 2026-08-18T00:00:00Z Xiaorang GuoKun QinYanbin ChenCarsten TrinitisMartin Schulz

The Quantum Control Processor (QCP) bridges the gap between compiler toolchains and control electronics, and is responsible for translating compiled quantum circuits into executable instructions that directly manipulate qubits and handle measurement feedback. However, existing designs rely primarily on customized instruction sets, limiting design reuse and requiring significant effort to build supporting toolchains. Furthermore, efficiently addressing qubits and scheduling operations in highly scalable scenarios remains a critical challenge. In this work, we present a vectorized quantum control approach built upon the RISC-V Vector (RVV) engine with a quantum-oriented extension. Leveraging the high parallelism of RVV, our approach can address up to 128 qubits in a single instruction. We also embed parameterized rotation information into the instruction set, enabling dynamic tuning of gate rotations in hybrid quantum-classical programs. To support mid-circuit measurements, we design a hardware-based halt-resume protocol that resumes pipeline execution within 80 $ns$ of receiving the measurement result. Comprehensive evaluation using both RISC-V toolchains and FPGA prototypes demonstrates that our design achieves up to 2.52$\times$ speedup over the baseline in program execution time, with excellent scalability.

https://arxiv.org/abs/2607.00660 2026-07-01T00:00:00Z 2026-07-01T00:00:00Z Ze-An ZhaoHai-Feng ZhangTian-Le WangXiao-Yan YangPeng WangRen-Ze ZhaoSheng ZhangZhi-Fei LiYuan WuZi-Hao FuSheng-Ri LiuPeng DuanGuo-Ping Guo

High-fidelity quantum gates are essential for scalable quantum computation. However, at short durations, short-timescale waveform distortions break the time-reflection symmetry of control pulses, preventing the precise closure of cyclic evolution. This mechanism renders conventional symmetric protocols intrinsically over-constrained. Conventional strategies typically rely on smoothing the pulse envelopes or embedding the interaction pulse within a longer qubit pulse to bypass short-timescale distortions, which inevitably leads to a persistent speed-fidelity trade-off. To overcome this limitation, we introduce a cyclic control strategy based on parameter-space expansion, which restores controllability by incorporating an additional degree of freedom. We experimentally demonstrate this approach in a superconducting controlled-Z gate, achieving robust suppression of coherent errors without increasing gate duration, reducing the average coherent error from 0.27% to 0.12% across multiple two-qubit gates, as validated by cross-entropy benchmarking. Our results establish a general route to fast, high-fidelity cyclic quantum gates beyond the conventional speed-fidelity trade-off.

https://arxiv.org/abs/2606.31534 2026-06-30T00:00:00Z 2026-06-30T00:00:00Z Svitlana MatsenkoAmirhossein GhazisaeidiMarcin JarzynaMateusz KucharczykMikkel N. SchmidtKonrad BanaszekDarko Zibar

Practical hardware limitations, including finite transmitter and receiver filter lengths as well as the finite resolution of digital-to-analog and analog-to-digital converters, lead to mode mismatch and degrade the performance of continuous-variable quantum key distribution systems. To address this, we develop a machine learning-based end-to-end optimization framework that jointly optimizes transmitter pulse shaping and receiver matched filtering. The approach employs reinforcement learning under realistic hardware constraints, including a limited number of filter taps, finite digital-to-analog and analog-to-digital converter resolution, analog low-pass filtering, and the optimal mean photon number. By mitigating mode mismatch and accounting for implementation constraints, the proposed method improves overall system performance. Simulation results demonstrate enhanced secure key rates compared to conventional approaches, demonstrating the effectiveness of the proposed framework.

https://arxiv.org/abs/2606.07472 2026-06-05T00:00:00Z 2026-06-05T00:00:00Z Julian D. TeskeRemy L. DelvaShobhan KulshreshthaYuval BaumFlorian LuthiFahd A. MohiyaddinRostyslav SavytskyyThomas WatsonPranav Mundada

The implementation of high-fidelity quantum gates for spin qubits requires accurate control of exchange interactions between electrons confined in quantum dots, but pulse distortions can limit this control accuracy. Although linear-dynamical distortions can be compensated for by appropriately convolving the control signal, determining the necessary convolution requires detailed knowledge of the distortion's transfer function, and therefore the calibration of numerous parameters. Alternatively, control pulses can be designed to have a net-zero time integral canceling out linear-dynamical pulse distortions. We generalize net-zero pulse designs to quasi-zero pulses allowing net-positive but reduced time integrals. Using these pulse designs, we systematically develop complete gate sets for exchange-only qubits, and study the resulting tradeoffs between pulse duration, fidelity, and the required number of tunable parameters, both in simulation and experiment. We benchmark the optimized gate pulses on Intel's Tunnel Falls six-dot device and show they achieve fidelities similar to those obtained with a full filtering approach, with identical pulse durations and fewer tuning parameters. This reduction in complexity opens the door to fast and easily automated calibration schemes compatible with large-scale commercial quantum devices.

https://arxiv.org/abs/2605.22433 2026-05-21T00:00:00Z 2026-05-21T00:00:00Z Junpeng SheRuoyu YanZhizhen QinZhanyu LiZhongtao ShenZichao ZhouBin-Xiang QiLuming Duan

As trapped-ion quantum computing scales to larger qubit registers and more complex control protocols, classical control systems face a fundamental tradeoff: sub-microsecond board-level feedback requires tight hardware coupling, whereas maintainability and extensibility require clean, modular software abstractions. This paper presents QuCtrl-BELL (Bell), a compiler-driven software stack for trapped-ion quantum control. The design resolves this tradeoff by decoupling control flow -- including loops, branches, and synchronization -- from hardware state data. A Python-embedded domain-specific language (DSL) is lowered through a six-stage transpilation pipeline covering control flow graph (CFG) construction, static single-assignment (SSA) conversion, liveness analysis, and graph-coloring register allocation. The compiler generates deterministic distributed board-level programs and compact step-table data. A cross-board synchronization protocol supports feedback loops with latency below 700~ns without host intervention. Bell is deployed and evaluated on the QuCtrl-BELL platform (RISC-V + PXIe), demonstrating that a compiler-based infrastructure can provide programmability, deterministic timing, and modularity for scalable trapped-ion quantum control.

https://arxiv.org/abs/2605.15233 2026-05-13T00:00:00Z 2026-07-09T00:00:00Z Rylan Malarchick

Public access to pulse-level and control-electronics interfaces in commercial quantum computing has bifurcated. This paper proposes a six-axis rubric for measuring control-plane openness, the layer between gate-level circuit specification and physical control electronics, defined operationally so that the same evidence produces the same grade across vendors. The rubric is validated three ways: a blinded re-grading pass that tests whether the cited evidence and the level definitions alone reproduce the recorded grades, a boundary-case methodology that fixes where each level begins and ends, and a published grading protocol that lets others reproduce and contest any cell. A time-point comparison anchored on the February 2025 removal of pulse-level access from IBM hardware establishes that the rubric measures change rather than describing a snapshot. The rubric is applied to thirteen commercial vendors across superconducting, trapped-ion, neutral-atom, and photonic modalities as of May 1, 2026, and one of the three harms it detects is demonstrated through a reproduction-access audit of five pre-2025 IBM Qiskit Pulse experiments, carried through to a structural port to Rigetti Quil-T. The catalog ships as a machine-readable artifact under CC-BY-4.0 with per-cell source URLs (https://doi.org/10.5281/zenodo.20163276). The readings will go stale; the rubric is the contribution that survives them.

https://arxiv.org/abs/2605.02512 2026-05-04T00:00:00Z 2026-05-04T00:00:00Z Inbar SternbachKfir Rutman MosheAmit BeerSoumitra HazraSharly Fleischer

We demonstrate direct time-domain observation of l-doubling contributions in molecular rotational dynamics using shaped femtosecond laser pulses. By imposing a tailored spectral phase on the excitation pulse, we pre-compensate centrifugal distortion, which otherwise leads to temporally broadened, multi-cycle revival structures that obscure fine rotational features. A cubic spectral phase [Phys. Rev. A 107, 053108 (2023)] compresses selected revivals into near single-cycle events, in agreement with an analytic expression derived from molecular rotational constants, enabling predictive pulse design beyond numerical optimization. The resulting distortion-free revivals reveal temporally separated l-doubling contributions that remain unresolved in conventional impulsive alignment experiments. The method proves robust against experimental imperfections, including spatial light modulator discretization. While selective control of individual l-doubling components becomes feasible, here we focus on their direct observation in the time domain.

https://arxiv.org/abs/2604.21565 2026-04-23T00:00:00Z 2026-07-20T00:00:00Z Animesh PatraAnkur Raina

High-fidelity control of superconducting qubits requires carefully shaped microwave pulses to avoid several different kinds of error at once. This article is a pedagogical bridging text aimed at upper-level undergraduate and early graduate students who have completed an introductory quantum mechanics course and a first course in quantum computing or quantum information, but who have not yet encountered the physical implementation of qubit gates. We integrate physical intuition for pulse design, analytical gate-level descriptions, and practical hardware considerations into a single, derivation-driven narrative, with explicit learning objectives. We begin with simple pulse envelopes and their spectral properties, showing how finite bandwidth produces leakage outside the computational subspace. This motivates the derivative removal by adiabatic gate (DRAG) technique, which we derive explicitly using the Magnus expansion, obtaining a clear, order-by-order account of which physical error channel appears at which order and why DRAG's cancellation is necessarily incomplete. We discuss the practical hardware realities of control pulse generation, focusing on arbitrary waveform generators (AWG), local oscillators (LO), and IQ mixing. Finally, we extend the discussion to two-qubit operation via the cross-resonance gate, and interpret how driving the control qubit at the target qubit's transition frequency necessarily produces several unwanted interaction terms alongside the desired one, and how successive generations of pulse-engineering strategies have been designed to suppress them.

https://arxiv.org/abs/2604.20482 2026-04-22T00:00:00Z 2026-04-22T00:00:00Z Pau Dietz RomeroNermine ChaabaniLammert DuipmansAlessandro DavidFelix MotzoiStefan van WaasenLotte Geck

Electron shuttling is emerging as a key mechanism for enabling long-range coupling in scalable spin-qubit architectures. Bringing shuttling waveform generation into the cryostat can improve scalability, but imposes strict area and power constraints on the control electronics. Concurrently, shuttling in Si/SiGe is further limited by a spatially varying valley splitting that induces spin--valley mixing and degrades coherence. Here, we make three contributions that address these limitations jointly: (i) an end-to-end co-simulation framework that combines disorder-informed valley maps with transistor-level cryogenic circuit simulations including electronic noise; (ii) a fully integrated cryogenic shuttling-signal generator tailored to velocity modulation, enabling period-wise waveform shaping through discrete circuit settings stored in on-chip memory; and (iii) a noise-aware optimization procedure that tunes only these implementable circuit controls, using one of four discrete resistor settings per period, to generate high-fidelity shuttling sequences. Across simulated valley and noise realizations in our co-simulation framework, the optimized velocity-modulation waveforms improve transport performance, achieving an average shuttling fidelity of $99.99 \pm 0.007\%$ at $v_{\mathrm{avg}} = 20~\mathrm{m\,s^{-1}}$ over a distance of $10~μ\mathrm{m}$, while maintaining active analog power consumption in the tens of $μ\mathrm{W}$ during shuttling. This validates on-chip storage and replay of optimized control settings as a practical strategy to mitigate valley disorder in scalable shuttling architectures.

https://arxiv.org/abs/2604.15895 2026-04-17T00:00:00Z 2026-04-17T00:00:00Z Dharun VenkateswaranFelice Francesco TafuriYuanzheng Paul TanBruno Aznar MartinezAlisa DanilenkoLikai YangArnaud Carignan-DugasChristoph HufnagelRainer DumkePhilip KrantzEric T. Holland

Flux-tunable superconducting qubits rely on fast flux control pulses to implement two-qubit entangling quantum gates, a key building block for quantum algorithms. However, distortion effects introduced by non-ideal control electronics, parasitic components, and the cryogenic quantum chip response can all degrade the gate fidelity. We present a digital predistortion (DPD) framework for characterizing and then compensating for these distortions using a combination of infinite impulse response (IIR) and finite impulse response (FIR) filters. Experiments on a flux-tunable quantum processing unit (QPU) demonstrate a successful correction of step-response distortions on the flux-control line, with a compensated control signal showing only sub-percent deviations from the ideal target linear behavior. The demonstrated method enables automated rapid calibration of flux control channels for superconducting QPUs.

https://arxiv.org/abs/2604.14623 2026-04-16T00:00:00Z 2026-04-16T00:00:00Z Muhammad NadeemXiaolin Wang

This study maps the quantum landscape of superconducting diodes (SDs) \cite{nadeem23} onto the quantum technology architecture, which is currently constrained by fundamental challenges in control and scalability. In the existing non-integrated quantum technology hardware, control and scalability related issues emerge at two fronts: First, nonlinear and nonreciprocal circuit elements, which are essential building blocks for quantum processors, are often complex, bulky, and dissipative. Second, the temperature gradient between classical control electronics ($T_C\gtrsim$ K), which is also dissipative, and the quantum processor at cryogenic temperatures ($T_Q\sim$ mK) makes scalability even more challenging. The main focus is to reveal how the built-in nonlinearity, nonreciprocity, and quantum functionalities of SDs are significant for on-chip integrated circuit quantum electrodynamics (c-QED), enabling scalable integration of noise-resilient qubit and qubit-interfaces for efficient power delivery, coherent control and memory, high-fidelity readout, and quantum-limited amplification. To this end, this study will also shed light on how thermodynamic constraints and field effects can be harnessed within a quantum-enhanced SD platform, thereby enabling thermal compatibility between classical and quantum workflows, isothermal all-electrical control, and on-chip scalability. This perspective is expected to play a pivotal role in the advancement of superconducting circuit-based quantum hardware with temperature-matched classical, quantum, and hybrid workflows.

https://arxiv.org/abs/2604.11743 2026-04-13T00:00:00Z 2026-04-13T00:00:00Z Victor MarcenacTommy NguyenJulie ChenWeitao HeEnrique GarciaYuyang HanBethany E. MatthewsTiamike DudleyAndrew A. MounceKai-Mei C. FuMaxwell F. Parsons

Dynamical decoupling techniques are widely used to characterize and control the environments of solid-state quantum defects, enabling solid-state quantum memories and nanoscale quantum sensors. However, resolution is often limited by the timing granularity of control hardware, which can undersample narrow spectral features and distort extracted parameters. Here, we demonstrate sub-nanosecond timing control on an inexpensive FPGA-based platform by extending the open-source QICK (Quantum Instrumentation Control Kit) framework using a waveform-offset method. This approach achieves an effective timing resolution of 200~ps on an RF system-on-chip device without modification to the underlying hardware. We apply this capability to dynamical decoupling spectroscopy of nitrogen-vacancy centers in diamond, enabling precise extraction of hyperfine couplings of individual $^{13}\mathrm{C}$ nuclear spins and resolving spectral features that are otherwise undersampled. These results demonstrate that high-resolution, device-level characterization of spin-based quantum memories can be achieved using flexible, inexpensive control hardware, providing a scalable alternative to commercial arbitrary waveform generators.

https://arxiv.org/abs/2603.20646 2026-03-21T00:00:00Z 2026-03-21T00:00:00Z Sibasish MishraAritra SarkarSebastian Feld

The scalability of quantum computing in supporting sophisticated algorithms critically depends not only on qubit quality and error handling, but also on the efficiency of classical control, constrained by the cryogenic control bandwidth and energy budget. In this work, we address this challenge by investigating the algorithmic complexity of quantum circuits at the instruction set architecture (ISA) level. We introduce an energy-efficient quantum instruction set architecture (EQISA) that synthesizes quantum circuits in a discrete Solovay-Kitaev basis of fixed depth and encodes instruction streams using a sparse dictionary learned from decomposing a set of Haar-random unitaries, followed by entropy-optimal Huffman coding and an additional lossless bzip2 compression stage. This approach is evaluated on benchmark quantum circuits demonstrating over 60% compression of quantum instruction streams across system sizes, enabling proportional reductions in classical control energy and communication overhead without loss of computational fidelity. Beyond compression, EQISA facilitates the discovery of higher-level composable abstractions in quantum circuits and provides estimates of quantum algorithmic complexity. These findings position EQISA as an impactful direction for improving the energy efficiency and scalability of quantum control architectures.

https://arxiv.org/abs/2603.18977 2026-03-19T00:00:00Z 2026-03-19T00:00:00Z Diego MartinLuis H. ArnaldiKenneth TreptowNeal WilcerSho UemuraSara SussmanDavid I. SchusterGustavo Cancelo

Quantum computing experiments and testbeds with large qubit counts have until recently been a privilege afforded only to large companies or quantum technologies where scaling to hundreds or thousands of qubits does not require a substantial increase in quantum control hardware (neutral atoms, trapped ions, or spin defects). Superconducting and spin qubit testbeds critically depend on scaling their control systems beyond what a single electronics board can provide. Multi-board control systems combining RF, fast DC control, bias, and readout require precise synchronization and communication across many hardware and firmware components. To address this, we present XCOM, a network that synchronizes QICK boards and the absolute clocks governing quantum program execution to within 100 ps, free of drift and loss of lock. XCOM also provides deterministic, all-to-all simultaneous data communication with latency below 185 ns. Like QICK itself, XCOM is compatible with a broad range of qubit technologies and is designed to scale to large systems.

https://arxiv.org/abs/2603.18052 2026-03-17T00:00:00Z 2026-09-09T00:00:00Z Rylan Malarchick

Dense Lindblad propagation at the Hilbert-space sizes of near-term transmon control ($d = 3$, $9$, $27$) sits in a regime where cache boundaries, launch overhead, and fixed latency decide which hardware is useful, not peak arithmetic rate. This paper characterizes that regime on two x86 CPUs, two NVIDIA GPUs, and a low-cost FPGA. Each implementation is stated as an algorithm in $d$ with an idealized cost built from separately measured ceilings, and the measured gaps are attributed to specific mechanisms: thread fork/join, the strided read of the propagator, PCI Express (PCIe) transfers, and propagator re-upload. An end-to-end gradient-ascent (GRAPE-style) benchmark against released QuTiP 5.2.3 shows that fast propagation does not imply fast control optimization: the C path wins by up to two orders of magnitude at $d = 3$ but loses at $d = 27$, where the dense LU solve inside the Padé propagator build takes over $90\%$ of the cost. The FPGA contributes a deterministic-latency operating point, $95$ cycles per step at a stress-characterized $108$ MHz with zero cycle spread over $1000$ trials, and its Q1.15 fixed-point drift is measured on the device. The results are a map of operating regimes for the measured grid, with the propagator build, not propagation, as the dominant cost at the largest size.

https://arxiv.org/abs/2603.16203 2026-03-17T00:00:00Z 2026-03-17T00:00:00Z Junyi LiuYi LeeYilun XuGang HuangXiaodi Wu

Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.

https://arxiv.org/abs/2602.14165 2026-02-15T00:00:00Z 2026-02-15T00:00:00Z Deepak RLokendra KanawatJayadeep KPriyesh Shukla

This paper presents a comprehensive cryogenic analog signal processing architecture designed for superconducting qubit control and quantum state readout operating at 4 Kelvin. The proposed system implements a complete bidirectional signal path bridging room-temperature digital controllers with quantum processors at millikelvin stages. The control path incorporates a Phase-Locked Loop (PLL) for stable local oscillator generation, In-phase/Quadrature (I/Q) modulation for precise qubit gate operations, and a cryogenic power amplifier for signal conditioning. The readout path features a Low Noise Amplifier (LNA) with 14 dB gain and 8-Phase Shift Keying (8-PSK) demodulation for quantum state discrimination. All circuit blocks are designed and validated through SPICE simulations employing cryogenic MOSFET models at 180nm that account for carrier freeze-out, threshold voltage elevation, and enhanced mobility at 4 K. Simulation results demonstrate successful end-to-end signal integrity with I/Q phase error below 2°, image rejection ratio exceeding 35~dB, and symbol error rate below $10^{-6}$. This work provides a modular, simulation-validated framework for scalable cryogenic quantum control systems.

https://arxiv.org/abs/2602.05154 2026-02-05T00:00:00Z 2026-02-05T00:00:00Z Aaron HoytMeng WangFei HuaChunshu WuChenxu LiuMuqing ZhengSamuel SteinDrew RebarYufei DingTravis S. HumbleAng Li

QASMTrans is a lightweight, high-performance, C++-based quantum compiler that bridges abstract quantum algorithms to device-level control and is designed for just-in-time (JIT) deployment on QPU testbeds with tightly integrated FPGAs or CPUs. We focus on achieving fast transpilation times on circuits of interest, we find more than 100x faster compilation than Qiskit in some circuits with similar circuit quality, enabling transpilation of large, high-depth circuits in seconds. Unlike existing tools, QASMTrans offers end-to-end device-pulse compilation and direct quantum control integration with QICK, closing the gap between logical circuits and hardware control enabling closed-loop optimization. QASMTrans supports latency-aware Application-tailored Gate Sets (AGS) at the pulse level, identifying high-impact gate sequences on the circuit critical path and synthesizing optimized pulse schedules using pre-defined robust circuit ansatz. Validated through integrated QuTiP pulse-level simulation, this is found to significantly reduce execution latency and can improve final-state fidelity by up to 12% in some tested circuits. QASMTrans further implements device-aware, noise-adaptive transpilation that uses device calibration data for circuit placement on high-quality qubits and can focus on the circuit critical path to reduce transpilation-pass time while maintaining comparable fidelity. Additionally, it introduces circuit space sharing via calibration-aware device partitioning, enabling concurrent execution of multiple circuits or shots on a single QPU. Moreover, QASMTrans is entirely self-contained and has no external library dependencies, making it easy for practical deployment. By combining fast compilation, pulse-level control, and noise-aware optimization, QASMTrans enables real-time adaptive algorithms such as ADAPT-VQE and ADAPT-QAOA.

https://arxiv.org/abs/2512.12999 2025-12-15T00:00:00Z 2026-01-08T00:00:00Z Leonardo Bohac

Quantum random access memory (QRAM) is a central primitive for coherent data access in quantum algorithms, yet it remains controversial in practice because the wall-clock cost of "one lookup" can hide routing depth, control overhead, and geometric constraints. We present a universal QRAM construction (U-QRAM) in which the database is a physical memory register that participates in the lookup unitary as quantum control. This yields a single fixed, data-independent lookup unitary on $A \otimes D \otimes M$ that is correct for all basis-encoded databases. Our first contribution is an explicit, exact Hamiltonian realization: U-QRAM equals a single time-independent evolution $U_{QRAM} = \exp(-iH_{tot})$ where $H_{tot}$ is a sum of mutually commuting projector terms, one per memory cell, and the construction avoids control-dependent phase ambiguities. Our second contribution is an architectural sharpening: under unary (one-hot, mode-addressed) encoding of the address, each cell term becomes uniform and 3-local, delineating the most direct path toward constant-latency interpretations. We keep claims conservative by separating latency from work and stating explicit hardware assumptions required for constant wall-clock queries.

https://arxiv.org/abs/2512.10706 2025-12-11T00:00:00Z 2025-12-11T00:00:00Z Chuanlong MaJia-Qi WangLinze LiJiajun ChenXiaoxuan PanZheng-Hui TianZheng-Xu ZhuJia-Hua ZouDingran GuLuyu WangQiushi ChenWeiting WangXin-Biao XuChang-Ling ZouBaile ChenLuyan Sun

Superconducting quantum computing has the potential to revolutionize computational capabilities. However, scaling up large quantum processors is limited by the cumbersome and heat-conductive electronic cables that connect room-temperature control electronics to quantum processors, leading to significant signal attenuation. Optical fibers provide a promising solution, but their use has been restricted to controlling simple two-level quantum systems over short distances. Here, we demonstrate optical control of a bosonic quantum processor, achieving universal operations on the joint Hilbert space of a transmon qubit and a storage cavity. Using an array of cryogenic fiber-integrated uni-traveling-carrier photodiodes, we prepare Fock states containing up to ten photons. Additionally, remote control of bosonic modes over a transmission distance of 15 km has been achieved, with fidelities exceeding 95%. The combination of high-dimensional quantum control, multi-channel operation, and long-distance transmission addresses the key requirements for scaling superconducting quantum computers and enables architectures for distributed quantum data centers.

https://arxiv.org/abs/2511.22537 2025-11-27T00:00:00Z 2026-09-28T00:00:00Z Kinnari DaveLouis LemonnierRomain PéchouxVladimir Zamdzhiev

The two main notions of control in quantum programming languages are often referred to as "quantum control" and "classical control". With the latter, the control flow is based on classical information, potentially resulting from a quantum measurement, and this paradigm is well-suited to mixed state quantum computation. Whereas with quantum control, we are primarily focused on pure quantum computation and there the "control" is based on superposition. The two paradigms have not mixed well traditionally and they are almost always treated separately. In this work, we show that the paradigms may be combined within the same system. The key ingredients for achieving this are: (1) syntactically: a modality for incorporating pure quantum types into a mixed state quantum type system; (2) operationally: an adaptation of the notion of "quantum configuration" from quantum lambda-calculi, where the quantum data is replaced with pure quantum primitives; (3) denotationally: suitable (sub)categories of Hilbert spaces, for pure computation and von Neumann algebras, for mixed state computation in the Heisenberg picture of quantum mechanics.

https://arxiv.org/abs/2511.14746 2025-11-18T00:00:00Z 2025-11-18T00:00:00Z Maxime Lapointe-MajorBoyan T. TorosovBohdan KulchytskyyPooya Ronagh

We present a gradient-based method to construct memory-efficient, high-fidelity, single-qubit gates for fluxonium qubits. These gates are constructed using a sequence of single-flux quantum (SFQ) pulses that are sent to the qubit through either capacitive or inductive coupling. The schedule of SFQ pulses is constructed with an on-ramp and an off-ramp applied prior to and after a pulse train, where the pulses are spaced at intervals equal to the qubit period. We reduce the optimization problem to the scheduling of a fixed number of SFQ pulses in the on-ramp and solve it by relaxing the discretization constraint of the SFQ clock as an intermediate step, allowing the use of the Broyden-Fletcher-Goldfarb-Shanno optimizer. Using this approach, gate fidelities of 99.99 % can be achieved for inductive coupling and 99.9 % for capacitive coupling, with leakage being the main source of coherent errors for both approaches.

https://arxiv.org/abs/2511.02249 2025-11-04T00:00:00Z 2025-11-04T00:00:00Z Tianqi CaiChitong ChenKunliang BuSainan HuaiXiaopei YangZhiwen ZongYuan LiZhenxing ZhangYi-Cong ZhengShengyu Zhang

Precise control of superconducting qubits is essential for advancing both quantum simulation and quantum error correction. Recently, transmon qubit systems employing the single-transmon coupler (STC) scheme have demonstrated high-fidelity single- and two-qubit gate operations by dynamically tuning the effective coupling between qubits. However, the integration of STCs increases the number of control lines, thereby posing a significant bottleneck for chip routing and scalability. To address this challenge, we propose a robust control line multiplexing scheme based on a double-transmon coupler (DTC) architecture, which enables shared coupler control lines to substantially reduce wiring complexity. Moreover, we experimentally verify that this multiplexed configuration efficiently suppresses undesirable static $ZZ$ coupling while maintaining accurate control over two-qubit gate operations. We further demonstrate the feasibility of the architecture through two distinct gate implementations: a fast coupler $Z$-control-based CZ gate and a parametric iSWAP gate. To validate the practical applicability of this multiplexing approach in quantum circuits, we prepare Bell and three-qubit GHZ states using the proposed scheme with fidelity exceeding 99% and 96%, respectively. This multiplexed DTC architecture offers significant potential to minimize wiring overhead in two-dimensional qubit arrays, thereby greatly enhancing the scalability of superconducting quantum processors.

https://arxiv.org/abs/2509.18482 2025-09-23T00:00:00Z 2025-09-23T00:00:00Z Yuanzheng Paul TanYung Szen YapLong B. NguyenRangga P. BudoyoPatrick BoreKun Hee ParkChristoph HufnagelRainer Dumke

Meaningful quantum computing is currently bottlenecked by the error rates of current generation Noisy Intermediate Scale Quantum (NISQ) devices. To improve the fidelity of the quantum logic gates, it is essential to recognize the contributions of various sources of errors, including background noise. In this work, we investigate the effects of noise when applied to superconducting qubit control pulses to observe the dependency of the gate fidelity with the signal-to-noise ratio (SNR). We propose a model on how the noise of the control electronics interacts with the qubit system and demonstrate a method for characterizing the noise environment of the qubit control.